`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:55:47 03/05/2013
// Design Name:   tff
// Module Name:   C:/Users/jimmy/Documents/2013/CSE 320/lab1/tff/tb/tb_tff.v
// Project Name:  TogFF
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: tff
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_tff;

	// Inputs
	reg toggle;
	reg clk;
	reg reset_b;

	// Outputs
	wire t_out;

	// Instantiate the Unit Under Test (UUT)
	tff uut (
		.toggle(toggle), 
		.clk(clk), 
		.reset_b(reset_b), 
		.t_out(t_out)
	);

	initial
	begin
		clk = 1'b0;
		toggle = 1'b0;
		reset_b = 1'b0;
		forever #5 clk <= ~clk;
	end

initial
	begin
	
#0;
	
	
#21 	reset_b <= 1'b1;
#1		toggle <= 1'b1;
#11	toggle <= 1'b0;
#5		toggle <= 1'b1;
#18	toggle <= 1'b0;
		
		#100;
		$stop;
	end
endmodule
